This application claims the priority benefit of Taiwan application serial no. 90129018, filed Nov. 23, 2001.
1. Field of Invention
The present invention relates to a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a memory device having a buried source/drain region and the fabrication thereof.
2. Description of Related Art
The buried diffusion, e.g., the source/drain region or the buried line, is regularly formed by implanting a high dosage of arsenic ions or phosphorous ions into the substrate and has a sheet resistance usually larger than 50 ohm/cm2. Such a high sheet resistance will slow down the device. For example, the operation speed of a Mask ROM (mask read-only memory) or a NROM (nitride ROM) will be lowered if the buried bit-line having high resistance is used only.
Accordingly, a memory device having a buried source/drain region and the fabrication thereof are provided in this invention to lower the sheet resistance of the source/drain.
Another object of this invention is to provide a memory device having a buried source/drain region and the fabrication thereof. This method can serve to increase the maximum linewidth of the word-line since the sheet resistance of the source/drain can be lowered even if the buried source/drain region is smaller.
Another object of this invention is to provide a memory device having a buried source/drain region and the fabrication thereof to enhance the operation speed of the memory device.
According to the above-mentioned objects and others, the method of fabricating a memory device having a buried source/drain region in this invention is described as follows. A dielectric layer is formed on a substrate, then a word-line is formed over the substrate, following by a buried source/drain region formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion of the metal layer covering the buried source/drain region beside the word-line and crossing over the word-line. Since the metal layer is formed in parallel connection with the buried diffusion, the sheet resistance of the bit-line structure (metal layer+buried diffusion) is lower than before and the operation speed of the memory device is therefore increased.
This invention also provides a method of fabricating a Mask ROM device. In this method, a dielectric layer is formed on a substrate, then a plurality of buried bit-lines are formed in the substrate and a plurality of word-lines that crossing over the buried bit-lines are formed over the substrate. Afterward, a barrier layer is formed on the exposed surfaces of the word-lines, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion of the metal layer covering the buried bit-lines beside the word-lines and crossing over the word-lines. Next, a coding process is performed to form a plurality of coding regions in the substrate.
In addition, this invention provides a method of fabricating a NROM (nitride ROM) device. In this method, a plurality of buried bit-lines are formed in the substrate, then a trapping layer, such as an ONO (silicon oxide/silicon nitride/silicon oxide) structure, is formed on a substrate. After that, a plurality of word-lines crossing over the buried bit-lines are formed over the substrate, then a barrier layer is formed on the exposed surfaces of the word-lines and a metal layer is formed over the substrate. The metal layer is patterned to leave a portion of the metal layer covering the buried bit-lines beside the word-lines and crossing over the word-lines.
In the preferred embodiments of this invention, the method of fabricating a Mask ROM device having buried bit-lines is described. In this method, a gate insulator is formed on the substrate, then a plurality of gate structures, which are equal to the word-lines, are formed over the substrate. Subsequently, a barrier layer is formed on the exposed surfaces of the gate structures, then an inter-layer dielectric layer is formed over the substrate. A lithography and implantation process is performed to form a plurality of buried bit-lines in the substrate, then the exposed inter-layer dielectric layer is removed, following by a metal layer formed on the substrate. The metal layer is patterned to leave a portion of the metal layer covering the buried bit-lines beside the word-lines and crossing over the word-lines.
Since a metal layer is formed in parallel connection with the buried diffusion, the sheet resistance of the new conductive structure (metal layer+buried diffusion) is lower than before. Besides, since the sheet resistance of the bit-line can be lowered by the metal layer even if the buried bit-line is narrower, the maximum linewidth of the word-line can be increased and the operation speed can be enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.